1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a NAND flash memory device.
2. Description of Related Art
Recent rapid developments in the semiconductor field have resulted in electric appliances being lighter, thinner and smaller. Accordingly, demand for a single power source and low operational power is increasing with respect to semiconductor memory devices used inside electric appliances. However, some types of semiconductor memory devices, such as a flash memory device, use a voltage higher than the power voltage to program a memory cell or to verify a programmed memory cell. This higher voltage, which may be generated through a high voltage generating circuit, is supplied to word lines during programming and erasing operations.
FIG. 1 is a circuit diagram showing a high voltage switch and a cell string structure of a conventional NAND flash memory device. Referring to FIG. 1, a ground selection transistor GST, memory cells MC0˜MC31, and a string selection transistor SST are connected in series to form one cell string. The ground selection transistor GST is connected to a common source line CSL, and the string selection transistor SST is connected to a bit line BL. Gates of the memory cells MC0˜MC31 are connected to a high voltage switch 10. A string selection line SSL is connected to a gate of the string selection transistor SST, and a ground selection line GSL is connected to a gate of the ground selection transistor GST. When a block is selected, a word line driver (not shown) provides selection signals SS, S0˜S31 and GS having corresponding voltages to the lines SSL, WL0˜WL31 and GSL, respectively, through the high voltage switch 10.
The high voltage switch 10 consists of high voltage transistors HVTR0˜HVTR33, each of which is capable of enduring a high voltage. Sources of the high voltage transistors HVTR0˜HVTR33 are connected to the ground selection line GSL (HVTR0), the word lines WL0˜WL31 (HVTR1˜HVTR32) and the string selection line SSL (HVTR33), respectively. Drains of the high voltage transistors HVTR0˜HVTR33 are connected to the selection signals GS (HVTR0), S0˜S31 (HVTR1˜HVTR32) and SS (HVTR33), respectively. Gates of the high voltage transistors HVTR0˜HVTR33 in the switch 10 are connected in common to a block selection line BLKSEL. When a block is selected, the high voltage switch 10 is turned on and then transmits the selection signals (or their voltages) GS, S0˜S31 and SS to corresponding lines GSL, WL0˜WL31 and SSL, respectively. When a block is not selected, the block selection line BLKSEL is set to have a low level of 0V, so that the high voltage switch 10 is turned off.
FIG. 2 is a cross-sectional view of a high voltage transistor in a conventional high voltage switch, as illustrated in FIG. 1.
Although one high voltage transistor HVTRi is illustrated in FIG. 2, it is understood that the remaining high voltage transistors are configured the same as illustrated in FIG. 2. The high voltage transistor HVTRi is formed on a P-type substrate 20 as its bulk, and not on a pocket P-well where memory cells are formed. As illustrated in FIG. 2, a gate voltage VG, a source voltage Vs, a drain voltage Vd, and a bulk voltage Vss are supplied to corresponding terminals, respectively.
The gate oxide layer of the high voltage transistor HVTRi is relatively thick, so that insulation break-down and junction break-down do not occur due to high voltages applied to the high voltage transistor HVTRi. Further, the P-type substrate 20 is lightly-doped and used as a bulk of the high voltage transistor HVTRi. This means that a voltage supplied to the high voltage transistor HVTRi cannot differ from a voltage supplied to the P-type substrate 20. For this reason, the bulk of the high voltage transistor HVTRi is biased with a voltage (e.g., 0V) identical to that applied to the P-type substrate 20. In a conventional NAND flash memory, an erase verification operation is made to check whether threshold voltages of erased memory cells are shifted to an erase state, with 0V supplied to word lines.
A negative voltage must be applied to word lines in order to narrow a threshold voltage distribution of an erase state and/or to program memory cells, so that a threshold voltage is less than 0V. However, it is difficult to sufficiently apply a negative voltage to the word lines via high voltage transistors that are structured as illustrated in FIG. 2. For example, assuming that a ground voltage is applied to terminal Vss and a negative high voltage is supplied to terminal Vd, a PN junction between an N+ impurity region 21 (or a drain of high voltage transistor HVTRi connected to a word line) and a P-type substrate 20 (or P+ impurity region 22) are forward biased. Accordingly, it is difficult to transfer a sufficiently low negative voltage to the word lines.